From the time that L2 cache was implemented up through the Socket 7 systems, the cache was actually on the memory bus. Unfortunately, even though cache SRAMs could operate at faster speeds than the DRAM used for system memory, having it on the same bus forced designers to run them both at the same speed.

With the introduction of the Pentium Pro, Intel put the cache on its own bus, which they called the Back Side Bus (BSB). They then called the memory bus the Front Side Bus (FSB). By doing this, they could run the cache much faster than main memory, and reduce the latency (from the processor perspective) even more, which Intel called the Dual Independent Bus (DIB) architecture.

With the Pentium Pro, the SRAM cache was integrated into the processor package (not into the processor chip). This allowed them to run the cache at full processor speed because of the very short transmission lines, however it was also very expensive. In order to cut costs they developed the Single Edge Cartridge, which allowed them to put the cache controller and commodity SRAM cache onto the same package as the processor running either at 1/2 or full processor speed, depending upon the performance and pricing required. With a ½ speed cache, the latency is reduced to 8 processor cycles or less, which is a significant improvement over the single bus solution.

More recently, the L2 cache has been integrated into the chip, much like L1 cache. This cache runs at full speed, but the width is generally the same as the memory bus (64 bits for the Pentium). As a result of shrinking electronic circuitry, these caches may be as large as 256K and may soon grow even larger. Typical latency for integrated L2 cache is 3 or 4 processor cycles.

As can be seen from this, the closer the cache is to the processor the faster it can be run and the lower the latency. The downside of this is that the closer it is to the processor, the more expensive it becomes. The tradeoff is therefore cost versus performance benefit, where performance usually takes the back seat.