To be able to read these timing charts, an understanding of the various signals is necessary. Most of these signals perform the same function on SRAM and DRAM chips, while others are specific to a particular design. The signal is considered 'high' when a high voltage applied and 'low' when a low voltage is applied. A description of the most important signals is provided here.

Address - The address lines are used to select the specific cell(s) to be accessed. DRAM chips will have a smaller number of address lines than SRAM chips due to cost reasons (more pins means a larger package, which means a higher cost). An SRAM device will generally receive both row and column addresses at the same time, while a DRAM will receive first the row address, followed sometime later by the column address. This is one reason SRAM chips have a lower latency.

Row Address Strobe (/RAS) - This signal is specific to asynchronous DRAM chips, and is used to latch in the row address as well as initiate the memory cycle. When /RAS is low, it is considered 'active'. In order to begin a new cycle, the /RAS line must be held inactive for a specific period of time, called the precharge time (tRP).

Column Address Strobe (/CAS) - This signal is specific to asynchronous DRAM chips, and is used to latch in the column address and initiate the read or write operation (i.e., the actual read or write of the memory cell). Before a new column can be accessed, there is a specific amount of time that the /CAS line must be held inactive, called the column precharge time (tCP).

Write Enable (/WE) - This signal is common to both SRAM and asynchronous DRAM, and is used to choose between a read operation and a write operation. When the signal is low a write operation is indicated, and when high a read operation is desired.

Output Enable (/OE) - This signal is present on SRAM and asynchronous DRAM chips. During a read operation, this signal is used to prevent data from appearing on the output until the appropriate time. It is ignored for write operations.

Data Inputs and Outputs (DQ) - These pins (also called I/O pins) are where the data is input (for a write operation) or output (for a read operation). If the 'bit' is a 1 the signal will be high, and if a 0 it will be low. For read operations, the data appears only when the Output Enable signal is active (if the chip is /OE controlled)

Clock (CLK) - This signal is only present on synchronous parts (both SRAM and DRAM), and controls when input signals are latched in as well as when output signals appear on the output pins.

Command - This signal is specific to Synchronous DRAM, and is used to provide the function of /RAS, /CAS and /WE. The ACTIVE command is the equivalent of setting /RAS low, and PRECHARGE is analogous to setting /RAS high. The READ command is the equivalent of /CAS going low and /WE set high, while WRITE is similar to /CAS set low and /WE going low.

DQM - This is another SDRAM specific signal, which is equivalent to /OE for an asynchronous device.

Bank Activate (BA0, BA1) - This is still another SDRAM specific signal. It determines which bank is being accessed.

In most cases, a signal must be held for a specific period of time before it is considered 'stable', which is called the setup time. After the signal has stabilized, there is usually another period of time that it must be held to ensure the proper value is read, called the 'hold time'. These setup and hold times are usually indicated in the charts and values are given for them as part of the timing parameters.

What follows is a series of timing charts for read operations with some explanations. Note that every manufacturer will have a data sheet for their specific parts, and may have several timing charts for each type of operation. The examples here are not exhaustive, and are presented simply for illustrative purposes. You may want to download the data sheet for the specific memory chips on your module and refer to the timing diagrams for a more complete picture of the timings.