System bus speed is the speed at which the DRAM and CPU communicate, and might be though of as the speed limit of the system highway. This has been the primary method of gaining improved system performance since the beginning. In fact, before cache was utilized the bus speed was increased from 4.77MHz to 33MHz in a very short time (from the 8088 to the 80386). Though processor speeds were rapidly increasing, DRAM speeds were sufficiently fast for the bus speed to be equal to the CPU speed.

While the 80486 processor was originally released as a 25MHz and 33MHz processor, 50MHz, 66MHz, 100MHz and even 133MHz flavors were soon introduced. Lagging DRAM speeds limited the bus speeds to a maximum of 50MHz, which meant the processors had to be clock doubled, tripled or quadrupled to achieve the faster speeds. This introduced a significant speed mismatch, as the CPU would have two or three clock cycles for each memory clock cycle, making SRAM cache a very important part of the system design.

With the introduction of the Pentium(r) processor, a superscalar architecture was implemented so that it was possible to execute more than one instruction per cycle. In addition system bus speeds were increased to 60MHz and then 66MHz, requiring fast DRAMs, while rapid advances quickly pushed the processor speeds to beyond 200MHz, requiring CPU multipliers of 3x and larger.

System bus speeds have continued to increase, first to 75MHz (first implemented for Cyrix processors) then to 100MHz. Very soon the 133MHz bus speed will be implemented, and we can expect further bus speed increases beyond that.