The most intriguing portion of the 810's abilities lies in the integration process itself, particularly the speed enhancements of the elimination of some of the PCI bus' traditional responsibilities. The following diagrams and text offer visual cues as to how Intel has streamlined the process:
The Intel® 810 chipset is the first in a series of Intel chipset products to be based on the Accelerated Hub Architecture which removes the PCI bus as the main device interconnect. This new architecture provides each critical multimedia subsystem with a direct link to the chipset. For example, data can now move directly from an IDE storage device to memory through a 266MB/s i/o channel without PCI bus contention or bandwidth limitation. The dedicated links to IDE, audio, modem, and USB subsystems ensure deterministic access to/from memory providing improved performance, optimal concurrency, and previously unattainable audio/video isochrony.
It is this new chipset architecture that now enables platforms to deliver on the promise of legacy ISA elimination. By creating direct interfaces for traditional ISA & X-bus functionality, the overhead of legacy 5V ISA support can be effectively removed.
The I/O control portion of the Intel 810 chipset is implemented as a separate device in order to isolate platform elements that are common across market segments (and future Accelerated Hub Architecture based segment-specific chipset products).
Eliminating road blocks along the data path has always been the main goal of Intel's core logic engineers, the PCI bus itself was created to handle larger bandwidth peripherals and software almost 10 years ago.
With the advent of the Accelerated Hub Architecture, the PCI bus is removed from the picture for certain peripheral's communication routes, allowing a 100% speed improvement from PCI's native 133MB/sec data throughput level to AHA's 266MB/sec level.
